This invention relates to phase-locked loop circuitry including programmable components, and particularly to such circuitry, for use in a programmable logic device, where the programmable components can be used for other purposes.
It is known to incorporate phase-locked loop “PLL”) circuitry on programmable logic devices “PLDs”). For example, it has become common for PLDs to accommodate various input/output standards, some of which require very accurate high-speed clocks. One way of providing such clocks is to provide PLL circuitry on the PLD.
A basic PLL includes a phase-frequency detector “PFD”), a charge pump, a loop filter and a voltage-controlled oscillator “VCO”), connected in series. The input or reference frequency is one input to the PFD. The output of the VCO, which is the output of the PLL, is also fed back to another input of the PFD. If the feedback signal is not locked to the input reference signal, then the PFD output will be a signal (voltage) whose sign is indicative of whether the output leads or lags and whose magnitude is indicative of the amount of lead or lag. That signal is filtered by the charge pump and loop filter and is input to the VCO, causing the output frequency to change. Eventually, the output signal will lock to the phase of the input reference signal. In this simple example, the output signal also will lock to the frequency of the input reference signal, but in most PLLs, counters on the input and output of the PLL are used to divide the input frequency, while a counter/divider in the feedback loop is used to multiply the input frequency. Thus the frequency of the output signal can be any rational multiple of the input frequency, but will be phase-locked to the input frequency.
PLLs are thus relatively large and complex circuits, and providing PLLs on PLDs therefore either adds significant area to the PLD, or takes away area that could be used for programmable logic circuitry in a PLD of a given size. This is of particular concern because the PLLs that are provided may not be used in a particular user design, so that, as far as that user is concerned, the PLL circuitry is simply wasted. It would be desirable to be able to recapture that circuitry when it is not being used as a PLL.
Conversely, PLLs that are provided on a PLD typically are of a fixed design determined by the PLD manufacturer. However, for particular user designs, that fixed PLL design may not be suitable. Heretofore in such cases, the user had to either provide a PLL externally, or consume programmable logic resources on the PLD, which could have been put to other uses, to construct a PLL meeting the particular needs of the user design. It would be desirable to be able to provide more flexible PLL circuitry on a PLD.